Identifying Resistive Open Defects in Embedded Cells under Variations

Abstract Small Delay Faults (SDFs) due to weak defects and marginalities have be distinguished from extra delays process variations, since they may form a reliability threat even if the resulting timing is within specification. In this paper, it shown that these faults can still identified, corresponding defect cell deeply embedded into combinational circuit its observability restricted. The results of few delay tests at different voltages frequencies serve as input machine learning procedures which classify marginal or just slow variations. Several techniques are investigated compared with respect accuracy, precision, recall for sizes scales. classification strategies powerful enough sort out defective devices without major impact on yield.